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1. Field of the Invention
This invention relates generally to computer aided design systems and in particular to a network, for use with a test pattern generator of a computer aided design system, for simulating the operation of a three state bus.
2. Prior Art
A design for a digital circuit is typically tested by applying a sequence of known test vectors to the design using a computer based system. A test vector typically defines all the input signals to the circuit and the expected output signals for the given input signals. The main purpose of the test vectors is to help the designer verify that the design has been correctly manufactured.
However, for a complex circuit, the generation of test vectors is itself a very complex process. Typically, as part of a computer aided digital circuit design package, a test pattern generator is provided to automatically generate test vectors. For circuits containing three state elements, such as three state element 50 described below, test pattern generators may produce test vectors that in fact are not valid. Therefore, prior to using the test vectors, the user must validate the automatically generated test vectors. The validation may be done manually or perhaps using a simulator. In either case, validation of the test vectors for circuits containing three state elements is a time consuming process.
Three state element 50 (FIG. 1) has two input lines 10, 20, data input line 10, and control input line 20, and one output line 25. Data input line 10 is provided a data input signal D-1 with either a logic value of zero or one. When signal E-1 on control input line 20 is active, the logic level of signal D-1 is transferred through element 50 to output line 25. When signal E-1 on control input line 20 is inactive, output line 25 is at a high-impedance state. Thus, the output signal from three state element 50 can be in one of three states, logic zero, logic one, or high impedance.
In a digital circuit, three state elements are often used to construct three state busses such as bus 60 (FIG. 2). Three state elements 50-1, 50-2, . . . 50-n have data input lines 10-1, 10-2 . . . 10-n that carry data input signals D-1, D-2, . . . D-n, respectively. Similarly, control input lines 20-1 . . . , 20-n carry control input signals E-1, . . . E-n, respectively.
In the digital circuit, three state bus 60 performs a multiplexing function, i.e., only one data input signal D-i is selected and appears on output line 30 as bus output signal Z. There are at least two possible states of bus 60 which are undesirable. In the first state, two or more of control input signals E are active and as a result a contention occurs on bus 60 between the output signals from the active three state elements.
In the second state, all control input signals E-1, . . . E-n are inactive so that bus 60 floats at a high impedance state. Both of these states are typically unacceptable in a digital circuit.
Unfortunately, a test pattern generator in a computer based design system does not have a means for determining whether a given test vector results in either contention or floating of a three state bus. Typically, a computer-based test generation system, and therefore the test pattern generator, support a set of primitive logic elements such as AND, OR, NAND, NOR, NOT and buffer.
A digital design is represented by an interconnection of the primitive logic elements, i.e. a network within the computer system. These primitive logic elements can be used for a test pattern generator to form a structure for three state bus 60, but such a structure fails to detect either floating or contentions without examination of the test vectors. To eliminate examination of the test vectors for a three state bus in a test generation system, the test pattern generator of that system must eliminate any test patterns that result in either contentions or floating of the three state bus, i.e., the test pattern generator must produce only valid test vectors.
Since there is currently no means available to generate known valid test vectors for a circuit including a three state bus, the general recommendation is to avoid use of three state busses in a digital circuit design. However, such an approach is of no value to the digital circuit designer that wishes to use such a bus. Therefore, a means for representing a three state bus including means for assuring that a test vector does not result in either a contention or floating of the three state bus would greatly enhance the performance and versatility of computer based test generation systems.